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- CoreUpGrade Overview
- CoreUpGrade Tools
- Case Studies 1 Cost Reduction
- Case Studies 2 Performance Enhancment
- CoreUpGrade for a Processor Core
- CoreUpGrade Interfaces
- Verification


 

Core Interface Configuration Modes

In Multi-Core, Multi-Channel and Multi-Tasking designs there are various configurations in which the upgraded core interfaces with the sub-system. Both Mplicity’s CoreUpGrade-Netlist and CoreUpGrade-RTL tools support these various configuration modes through the tools creation of a configurable–wrapper, which maximizes the user-defined parameters according to the selected system interface methodology for a specific environment.

Independent Resource Configuration
In this approach each Virtual Logic Block requires its own resources. Following the CoreUpGrade process, all of the single logic block's I/Os are replicated. The busses, peripherals and memories are operating at the original frequency.  Each Virtual Logic Block then acts as a totally independent logic block capable of executing its own operations. When each of the logic blocks is a processor core, then  the cores after CoreUpGrade have same functionality as the original and each can run its own operating system and applications.

Shared Resources Configuration
In this configuration the Virtual Logic Block shares common resources. This dictates that both the interface and the external resources run at dual-rate frequency in order to enable communication between the resources and the virtual processors through the same buses.  Furthermore, an RTOS capable of executing multi-thread or scheduler for multi-tasking is required. Having achieved a virtual dual-core environment, the Virtual Logic Block now “believes” that it can process twice the number of transactions without degrading performance or speed. In essence, the system operates as a single logic block capable of executing multiple tasks.

Mixed Configuration
In a combined (Independent and Resource Sharing) configuration each Pin of the Virtual Multi Logic Blocks can be configured to work in two different modes, a Common Mode and an Independent Mode.

bull As part of the Common Mode – A common pin serves all Virtual-Multi-Logic-Blocks must run at a higher frequency.
bull Where as in the Independent Mode – Each pin serves a single Virtual Logic Blocks and therefore runs at the original frequency.