CoreUpGrade for a Processor Core
Mplicity’s CoreUpGrade technology and tools provides automatic performance and area optimization for new and existing Multi-Core designs, (a core being any combinatorial logic block). The patent pending automated tools seamlessly execute the proprietary CoreUpGrade technology transforming any symmetric, fully synthesizable logic including processor cores into either a Virtual Multi-Core or a Virtual Multi-Thread design. In both, instances silicon developers are able to obtain a significant performance increase, while reducing silicon die size and overall system power consumption all with the luxury of reusing and repackaging their existing cores into a new enhanced silicon design.
Area Optimization of Multi-Core Blocks
One of the major trends evolving in the silicon industry is the use of multiple processor cores to achieve performance coupled with power efficiency techniques to extend battery life. These ever escalating demands have made not only Moore’s law defunct but “old” approaches such as deepening the pipeline, out of order execution; super scalar and VLIW are also being phased out as the overhead associated with these concepts is much too high to be cost justifiable. And although Multi-Core systems enable an increase in performance by implementing multiple cores, they too suffer from higher costs because of the larger die area required for multiple cores. This being the case any increase in performance generally comes at a substantial increase in silicon cost and system power consumption and is precisely why Mplicity’s CoreUpGrade technology is needed, since CoreUpGrade provides ASIC and FPGA developers the tools and technology to design significantly higher performance, compact, power efficient systems.
Systems already comprised of multiple symmetric processor cores (such as Network, Storage and Multimedia Processor chips, etc) suffer relatively large die sizes, higher costs and longer interconnections.
Using the CoreUpGrade within a standard design flow, significantly reduces the area of the repetitive symmetric processor cores by eliminating (in a dual core environment) half of the processors by transforming each core into a Virtual Dual-Core. This effectively reduces by half the number of physical cores, although the system continues to view the same number of cores as found in the original design while maintaining virtually the same performance level.
Furthermore by replacing real cores with virtual cores the size and number of the interconnections can also be dramatically reduced which can translate into a significant reduction in overall system size and power consumption.
Since the original design is already comprised of multiple cores, the new Multi-Core Area Optimized design generated via execution of the CoreUpGrade process can run the same software (OS, and applications) without any modifications.
Increasing Processor Performance through an Automatic Virtual Multi-Core Tool Process (CoreUpGrade)
In those instances when a given processors MIPS are insufficient, the CoreUpGrade can transform a single-core design into a new Virtual Multi-Core design increasing performance by a factor of 2x, 3x or 4x.
The essential inputs for running the CoreUpGrade tool are a fully synthesizable Netlist/EDIF depicting a single block as well as the appropriate SDF file and cell libraries. Upon completion of CoreUpGrade phase, the standard EDA design flow continues utilizing the new enhanced Netlist/EDIF. One of the major benefits newly generated CoreUpGrade IP is the tremendous improvement in the performance to silicon area ratio, in some cases as much as an 83% increase in performance with only a 19% area increase. Other benefits derived from Mplicity’s CoreUpGrade technology are that the core's input and output ports are the same as the original core's ports, and the software model of the new virtual cores is exactly equivalent at the binary code level thereby enabling any software code running on the new processor to be executed just as it was in the original processor environment.
Software Implications of Transforming a Single-Processor Design to a Dual or Multi-Core design.
There are often software implications associated with transforming a single-processor design into a Dual-Core or Multi-Core design that are a direct result of increasing performance through the creation of new processors in the design.
When using the CoreUpGrade process, concurrent multiple instruction streams are required by the upgraded processor. This is necessary to achieve the increased CoreUpGrade performance increment benefits attainable by each Virtual Processor.
One approach is to allow each Virtual Processor to run its own specific code, while another approach is to split the existing application code into several loosely coupled blocks. In those applications where the partitioning is part of the algorithm, the splitting process is an easy task. In other cases, a multiprocessor operating system needs to be used to manage the running applications and share the common chip resources.
