Cost Reduction

Mplicity's CoreUpGrade Concept Reduces Die Size of MultiCore Designs
Designers know that by implementing a multi-core architecture that replicates large blocks of repetitive logic and/or the number of processors, they may be able to achieve their performance goals. But, they are also fully aware that by using the traditional 1+1+1 approach they will detrimentally affect their chip design with respect to die size as well as costs. This is precisely why silicon vendors continue to seek-out technologies that will allow them to seamlessly migrate to next generation products while maintaining full cycle-by-cycle object code compatibility, enhancing performance and reducing die size, power, costs and time-to-market constraints.

In this example, the chip design incorporates two original cores, each running at 260MHz, giving an actual performance level of 520MHz. The CoreUpGrade process reverts to a single core design (from physical point of view), but transforms the single core into a virtual dual-core environment. In this case, the performance at the end of the process is at the same level, but the die area required for the cores is now 50% of the original area required for the 2 physical core solution. In essence, a 50% reduction has been achieved in the core die size and corresponding silicon cost, with only a 10% reduction in performance.