CoreUpGrade Tools
Mplicity’s CoreUpGrade tools are designed to address silicon vendors needs to provide more powerful, compact and efficient chips. This is accomplished using either the CoreUpGrade tools proprietary command line interface and associated scripts, or through a GUI-driven environment where a console of drop down menus and fields is presented for the users selection.
The CoreUpGrade process is an automatic process executed on a single logic block and based on user-defined configuration criteria. The culmination of running this process by the CoreUpGrade tool is an enhanced Virtual-Multi-Logic-Block design, representing a new block, were each of the virtual logic blocks is fully compatible with the original single block.
The CoreUpGrade tools automatically generate a configurable wrapper which determines the subsystem connectivity of each design input and output as well as its impact on chip performance and die size. In those instances where the CoreUpGrade is used to enhance design performance the design's input and output ports remain the same as in the original design, however the new design is now capable of executing multiple task simultaneously. Alternatively, when the CoreUpGrade focuses on reducing chip costs the repetitive logic block instances are replaced a virtual repetition of the logic blocks and needs to maintain the exact inputs and outputs.
The software model of the enhanced logic block is exactly equivalent to the original logic block (at the binary code level), enabling any software code running on the new design to be executed just as it was in the original design environment. However, the throughput will be much higher, since two (or up to 4) virtual logic blocks can be fused within the same footprint.
At the tool configuration stage, engineers are able set parameters through a script file or the GUI. They can also set at this time the process invocation switch which is used to select the number of Virtual Multi Logic Block to be duplicated. Currently the process invocation switch can be set anywhere from 2x up to 4x, in single multiple increments. It is also possible to utilize additional input files that supply critical information with respect to timing constraints and other specific user-defined cell information. Furthermore, ports or cells earmarked for duplication can be selected, as well as design false-paths and multi-cycle paths. Once all of the desired criteria have been selected a single execution command is required complete the configuration stage and run the CoreUpGrade process.
To operate the CoreUpGrade automatic process, Mplicity provides two possible flows:
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Hannibal Tool - Gate Level Flow that process Netlist and EDIF |
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Genghis-Khan Tools - RTL Flow that process Verilog and VHDL |
CoreUpGrade Gate Level Flow:
The CoreUpGrade Gate level flow is a simple, fast and accurate process of enhancing a design by implementing Mplicity's proprietary technology. This flow enable customers to enhance an existing design without the need of re-synthesizing the design.
Engineers can easily operate the Hannibal tool. using either the command line interface and scripts or the GUI-driven environment, The Hannibal tool works at the Netlist or EDIF gate level, and interfaces with all standard industry formats and synthesis tools. To perform the CoreUpGrade process on an ASIC, the standard Netlist, SDF and lib (standard cells liberty format) files of the design are required; on an FPGA, the EDIF, SDF file and lib of the cell libraries are required.
CoreUpGrade RTL Flow
Mplicity developed an RTL to Enhanced-RTL conversion, which transforms a single logic block into Virtual-Multi-Logic-Block enabling customers to upgrade their existing as well as new designs while utilizing traditional synthesis and verification EDA flows.
Two tools comprise the RTL flow:
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Genghis – which transform a single logic block RTL into Virtual-Multi-Logic-Blocks RTL |
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Khan – which is a gate level optimizer |
The Genghis tool is an RTL to Enhanced-RTL transformation that converts a single logic block into a Virtual-Multi-Logic-Block. After that, a synthesis is done by using any off the shelf EDA synthesis tools. Then, the Khan tool performs optimization phase to improve the timing and area results according to the physical implementation.
The Genghis tool inputs are Verilog or VHDL files, execution scripts file and I/O constrains flies. The Khan tools’ inputs are Netlist or EDIF files, execution scripts, standards SDF and lib files.
