CoreUpGrade Overview

Mplicity’s CoreUpGrade proprietary algorithms and tools are designed to allow customers to realize the most from new and existing core logic blocks as well as differentiate their mission critical projects by adhering to key silicon cost, area and performance optimization targets which are instrumental if they are to achieve greater market share and generate increased revenues.   

Mplicity's CoreUpGrade tools have been specifically engineered to enhance developers existing and new designs by automatically executing the CoreUpGrade algorithms that allow for the creation of a virtual 3D pipeline and transform single logic block/s into Virtual-Multi-Logic blocks. 

Being process and library independent the CoreUpGrade can be used in any ASIC, FPGA  or SoC flow and is ideally suited for those embedded systems (e.g. communications, networking, storage, multimedia etc…)  requiring increased performance and die size optimization.  Developers in this space utilizing the CoreUpGrade process directly benefit from an:

Area Reduction
Many of the aforementioned multi-channel products require massive parallel processing which designers typically attempt to achieve by replicating the original logic block/s an unwarranted number of times to create a multi-channel system, the outcome being a faster but also an enormously larger chip. Conversely, Mplicity’s CoreUpGrade reduces the die size of the repetitive logic blocks, by automatically creating a Virtual-Multi-Logic-Block implementation replacing the multi-logic block configuration.

An example of unnecessarily replicating the same logic block is easily found within a 1024 VoIP channel design that was composed of a 1024 instantiation of single VoIP channel,  Utilizing Mplicity’s CoreUpGrade technology in a virtual dual core mode it would be possible to placed in 1024 channel in an area equivalent to 512 channels.

 In another example, a Dual-Core system, where the same logic is instantiated twice, can be replaced by the CoreUpGrade with a virtual dual core that is half the size of an equivalent single core thereby reducing system die size and power consumption.

Performance Enhancement
When using the CoreUpGrade technology to enhance performance the tools automatically transform a given single logic block (of any type including processors) into a Virtual-Multi-Logic-Block with each of the virtual logic blocks having the same functionality and performance as the original single logic block.
The number of the virtual logic blocks created via the tools permits more design IP reusability and  directly impacts the attainable system performance increase.

Depicted below is the transformation of  a single logic block into a Virtual-Multi-Logic-Block, using Mplicity's CoreUpGrade tools, which enables the execution of two or more tasks simultaneously, either as a multi-tasking or multi-threaded design.

 

 

 

 

In addition Mplicity’s CoreUpGrade technology maintains the watt per MIPS ratio and can even reduce overall system power consumption.