Mplicity’s Hannibal tool introduces a new capability to FPGA Multi-core designs flow that enables the use of smaller/cheaper FPGA devices, thus reducing the cost of their solutions. In many applications that utilize FPGAs, such as communication processors (multi-channel) and storage processors, there is a need for more performance that is typically achieved by using repetitive logic. Mplicity's CoreUpGrade can dramatically reduce the LUT utilization of these designs, which is typically the device bottleneck.

Single Leon3:

	Device		xc4vsx35
	LUT Utilization		65%
	Critical path		16.966ns

Two instantiation of original Leon3 design:

	Device		xc4vsx55
	LUT Utilization		81%
	Critical path		16.786ns

Dual virtual Leon3 – after CoreUpGrade:

	Device		xc4vsx35
	LUT Utilization		79%
	Critical path		10.5ns

Single Leon VS Dual Virtual Leon

Utilizing the same device (xc4vsx35) the performance is improved by 61.6%

Dual instantiation of original design VS Dual virtual Leon

	Using two level smaller device (35 instead of 55) the performance reduced only by 25%
	Using one level smaller device (40 instead of 55) the performance is reduce by only 19%

Leon3 is a product of Gaisler