Designers know that by implementing a multi-core architecture that replicates large blocks of repetitive logic and/or the number of processors, they may be able to achieve their performance goals. But, they are also fully aware that by using the traditional 1+1+1 approach they will detrimentally affect their chip design with respect to die size as well as costs. This is precisely why silicon vendors continue to seek-out technologies that will allow them to seamlessly migrate to next generation products while maintaining full cycle-by-cycle object code compatibility, enhancing performance and reducing die size, power, costs and time-to-market constraints.

In this product, the chip design incorporates two ARC 625D cores, each running at 270MHz, giving an actual performance level of 540MHz. The CoreUpGrade process reverts to a single core design (from a physical point of view), but transforms the single ARC-625 core into a virtual dual-ARC625 core environment. In this scenario the performance at the end of the CoreUpGrade process is at a similar level of two cores, but the area required for the cores is considerably smaller than the original area required by two physical cores.  The benefits derived by utilizing Mplicity CoreUpGrade technology were a significant die size area reduction and corresponding silicon cost reduction with only a 13% performance penalty. The overall performance per area ratio using Mplicity’s solution yielded a  27.5% improvement.

ARC-625D is a product of ARC