Mplicity’s RTL CoreUpGrade flow is based on the Genghis-Khan tool set.

The CoreUpGrade flow interfaces with the standard industry formats supported by all of the EDA tools and engineers can easily operate the CoreUpGrade RTL process either through its command line interface or via GUI-driven environment..

The RTL flow as depicted below is comprised of two tools Genghis and Khan.

 

Genghis automatically transforms a single logic block RTL into Virtual-Multi-Logic-Blocks RTL.  , while Khan performs automatic gate level optimization

The Genghis tool converts the RTL code describing any single logic block into a Virtual-Multi-Logic-Block RTL as well as creating a wrapper of the enhanced design according to user defined subsystem requirements.
The wrapper is used to determine if the enhanced design functions as a multi-tasking / multi-threading (for performance enhancement) design or as a multi-core / multi-channel (for cost reduction) design. The tool creates virtual processing elements for the new Virtual-Multi-Logic-Block all with the same functionality and performance as the original logic block thereby allowing for a significant design performance, since instead of single logic block there are multiple virtual-replications of the same instance.

The users can synthesis the enhanced RTL by using standard EDA off the shelf synthesis tools, then the Khan tool can be used to perform optimization by phase in improving the timing and area results according to the desired physical implementation. It is possible to further optimize the design by using the Khan tool can in iterative back-annotation flow.

The input elements for Genghis are standard Verilog or VHDL files, execution scripts file and I/O constrains flies where as the Khan tool inputs are Netlist or EDIF files, execution scripts, standards SDF and lib files.    

Through inherent logic buffering techniques and the elimination of large logic blocks signal toggling there will be a significant power dissipation reduction. In addition, when an upgraded core is compared with an equivalent multi-core solution, there is an obvious power consumption reduction due to a silicon size reduction. Taking all of this into account, along with providing a highly optimized system integration solution, a significant overall system power consumption saving can be achieved.

The Genghis tool operation
The following is the Khan tool operational stages

Step 1 - File Parsing

The first stage of the Genghis tool is to parse the execution script or receive them through the GUI.  Then it read the design files and design timing constrains files according to an execution script and imports them into an internal database. The following inputs are required for the tool operation:

	A fully synthesizable Verilog or VHDL: Describes the block that needs to be enhanced by the CoreUpGrade.
	Timing Constraints: input and output design constrains

Step 2 - Link and setup environment

The Genghis tool process the database link the design hierarchy and determines the top-module. Then the tool creates the design connectivity. Then the tool set environment variables and objects that required for tool operation.

Step 3 - CoreUpGrade Elements Insertion

The Genghis tool then insert the CoreUpGrade elements to transform it into Virtual-Multi-Logic-Block. Since there is no physical information at HDL level, the tool cannot place these elements in optimal position and thus the enhanced HDL needs to further be optimized by using the Khan tool. The enhanced HDL can be used for simulation, verification and synthesis as traditional HDL.

Step 4 - Print Result Files

At the last operational stage, the Genghis tool prints the results files that include:

	The new enhanced Verilog / VHDL
	Reports of the process warning, errors and information

The Khan tool operation
The following is the Khan tool operational stages:

Step 1 - File Parsing

   

The first stage of the Khan tool is to parse the execution script or receive them through the GUI.  Then it read the design files, design-timing files and design timing constrains files according to an execution script and imports them into an internal database. The following inputs are required for the tool operation:

	A fully synthesizable Netlist or EDIF: Describes the block that needs to be enhanced by the CoreUpGrade.
	Standard SDF file: Describes the cells and inter-connection timing.
	Standard Cells Library file: Describes the cells functionality.
	Timing Constraints: input and output design constrains.

Step 2 - Link and setup environment

The Khan tool process the database link the design hierarchy and determines the top-module. Then the tool creates the design connectivity and maps each of the module/gates to the library cell. The tool also processes the design timing data and maps it to design gates, modules, block-boxes and wires. Then the tool set environment variables and objects that required for tool operation.

It is possible to save current database file (.BD) for future tool re-run.

Step 3 – Static Timing Analysis (STA)

After the database is ready, the Khan tool performs static timing analyzing and updates the database according to timing I/O constrains. The tool calculates the forward and backward timing and determines the critical path and accordingly. The tool also calculates the expected I/O timing constrains at the end of the CoreUpGrade process.

Step 4 – CoreUpGrade Elements Optimization

The tool performs the CoreUpGrade element timing and area optimization. After STA the tool has complete mapping of design timing, it then can determined region of opportunity of where is the best place to reposition the CoreUpGrade elements. Any point within this region is a valid potential point to place the element without harming the timing results of the upgraded design.

Through the element repositioning proprietary optimization algorithms, supporting a variety of design topologies and technologies, the CoreUpGrade determines and implements the CoreUpGrade elements repositioning in the most optimized way, resulting in the minimum number of element.

Step 5 – Print Result Files

At the last operational stage, the Khan tool prints the results files that include:

	The new enhanced Netlist / EDIF
	Reports of the process warning, errors and information
	I/O constrains files for the enhanced design
	Information for formal verification tools