The inputs for the CoreUpGrade gate level process are a fully synthesizable Netlist/EDIF file along with the corresponding SDF and configuration files.  The  Hannibal tool uses these inputs to transparently transform single logic block/s into an enhanced Virtual-Multi-Logic-Block/s and is automatically executed based on user-defined configuration criteria.

A process invocation switch determines the desired improvement factors;  2x, 3x, or 4x and controls the number of virtual blocks created .

The output generated at the end of the CoreUpGrade process is a Virtual-Multi-Logic-Block standard Netlist or EDIF file which serves as the basis for the remainder of the standard EDA design flow.  The new enhanced Netlist/EDIF file that was created via execution of the CoreUpGrade process is fully compatible with the original logic block.

The enhanced design's input and output ports are the same as the original design's ports, and the software model of the new design is exactly equivalent (at the binary code level), to the original, enabling any software code running on the new design to be executed just as it was in the original.

When converting via the CoreUpGrade process a single logic block (e.g. single-processor or single channel) into a Virtual-Multi-Logic-Block it can be viewed by the system as either distinct multi-logic blocks or a multi-tasking design

In a multi-tasking environment, the enhanced logic block processess several tasks in parallel, thus replacing the slow sequential logic which runs tasks sequentially. In order to take full advantage of the enhanced processing performance achieved by  the creation of a CoreUpGraded multi-tasking processor it is necessary to increase the program and data memory speeds as well as running a Real Time Operating System.

When the CoreUpGrade process is used to substitute multiple logic instances through the creation of an enhanced logic block it is possible replace an expensive large die size multi logic cluster with a considerably smaller logic block. Moreover it is possible to maintain full system pin compatibility with the original design and does not require the use of higher speed memories or a Real Time Operating System.

More info regarding the system connectivity can be found in CoreUpGrade Interfaces.

Through inherent logic buffering techniques and the elimination of large logic blocks signal toggling there will be a significant reduction  in power dissipation .  Futhermore,  when comparing an upgraded core with an equivalent multi-core solution there is an obvious power consumption reduction due to a silicon size reduction.

Taking all of this into account it is evident that Mplicity’s CoreUpGrade technology provides a highly optimized, power consumption efficient system integration solution.  

TBD (GIL) This is same as Khan just 4 is different

Hannibal Tool Execution
The following is the tool operational stages:
 

Step 1 - File Parsing

The first step is for the Hannibal tool to either parse the execution script or receive the script through the GUI.   It then reads the design files, design-timing files and design timing constrains files according to an execution script and imports these files into an internal database.

The following inputs are required for the tool operation:

Step 2 - Link and Setup Environment

The Hannibal tool processes the internal database,  links the design hierarchy and determines the top-module. The tool then creates the design connectivity and maps each of the module/gates to the library cell. It also processes at this stage the design timing data and maps it to design gates, modules, block-boxes and wires. At this juncture it is possible to input user defined timing variables that may be required for the tools operation and to save the current internal database file (.BD) for tool re-runs if necessary.

Step 3 - Static Timing Analysis (STA)

Once the internal database is ready, the Hannibal tool performs the static timing analysis and updates the database according to user-defined timing I/O constraints.  Hannibal then calculates the forward and backward timing and determine the critical path as well as. the expected new I/O timing constraints which will be reported at the end of the CoreUpGrade process.

Step 4 - Elements Insertion and Optimization

At this stage Hannibal initiates  the CoreUpGrade transformation which determines the regions of opportunity for element insertion. Any point within these regions is a valid potential point to place the insertion element and will not adversely impact the timing results of the upgraded design. The tool also automatically identifies all the design machine state registers and replaces them into patent pending MT-Cells that hold all the virtual blocks machine states, and the schedules between them ensuring efficient design upgrading while maintain single clock domains.

The element insertion proprietary optimization algorithms, support a variety of design topologies and technologies,

Step 5  - Print Result Files

Upon completion of the last operational stage the Hannibal tool prints the result files for: